Arachne-pnr implements the place and route step of the hardware compilation
 process for FPGAs. It accepts as input a technology-mapped netlist in BLIF
 format, as output by the Yosys synthesis suite for example. It currently
 targets the Lattice Semiconductor iCE40 family of FPGAs. Its output is a
 textual bitstream representation for assembly by the IceStorm icepack command.
 The output of icepack is a binary bitstream which can be uploaded to a hardware
 device.
 .
 Together, Yosys, arachne-pnr and IceStorm provide an fully open-source
 Verilog-to-bistream tool chain for iCE40 1K and 8K FPGA development.