iverilog 10.3-ok1 (amd64 binary) in openkylin yangtze

 Icarus Verilog is intended to compile all of the Verilog HDL as
 described in the IEEE-1364 standard. It is not quite there
 yet. It does currently handle a mix of structural and behavioral
 constructs.
 .
 The compiler can target either simulation, or netlist (EDIF).

Details

Package version:
10.3-ok1
Source:
iverilog 10.3-ok1 source package in openKylin
Status:
Deleted
Component:
main
Priority:
Optional

Package relationships

Provides:
  • verilog
Replaces:
  • verilog (<< 10.2-0)
Suggests:
Breaks:
  • verilog (<< 10.2-0)